* Analysis of Sequential Circuits * Excitation Tables for Flip Flops * Finite State Machine Diagram * Mealy Finite State Machine * Moore Finite State Machine * Need for State Machines * State Diagrams * State Encoding Techniques * State Machine * State Minimization * VHDL Coding of FSM * JK flipflop State Machine * Metastability measurement setup * Metastability Synchronizer * Detection of Static Hazards * Dynamic Hazards * Effects of Hazards * Elimination of Static Hazards * Static Hazards * UART Transmitter Design * UART Receiver Design * Traffic Light Controller * Simple Traffic Controller * Serial Adder * Sequential Counters JKFF * Sequential Counters DFF * Sequential Counters * Sequence Generator * Sequence Detector * Lift Controller * Analysis of Asynchronous Sequential Machines * Asynchronous FSM * Design of Asynchronous Sequential Machine * Design Procedure for Asynchronous Sequential Circuits * Essential Hazards * Hazardfree circuit * Modes of Asynchronous Sequential Machines * ASM chart 2 bit up down counter * ASM chart for signal generator * ASM charts * ASM Chart Tool for Sequential Circuit Design * Design with Multiplexers * adjustable negative voltage regulator ics * current booster * dual power supply * low drop out voltage regulators * series regulator using op amp * three terminal adjustable voltage regulator ics * three terminal fixed voltage regulator ics * voltage regulators ics * asymmetrical inverting schmitt trigger * inverting schmitt trigger * non inverting schmitt trigger * modified precision full wave rectifier * non saturated type precision half wave rectifier * precision full wave rectifier * saturating type precision hwr * difference integral * non inverting integrator * practical integrator * summing integrator * practical differentiator * summing differentiator * comparator as a duty cycle controller * comparator as a function generator * comparator ic lm 311 * inverting comparator * non inverting comparator * voltage controlled oscillator * window comparator * asymmetrical square wave generator * bistable multivibrators * monostable multivibrator * sawtooth waveform generator * triangular waveform generator * binary weighted resistor dac * counter type adc * dual slope type adc * flash type adc * r 2r ladder dac * successive approximation type adc Pull down network is made up of NMOS Transistors because of property of passing strong '0'Īs the mobility of PMOS transistor is lower than NMOS transistor, W/L ratio of PUN transistors is higherĪs the mobility of NMOS transistor is higher than PMOS transistors, W/L ratio of PDN transistors is Lower Pull up network is made up of PMOS Transistors because of property of passing strong '1' Pull down network is used to make output as Logic Low Pull up Network is used to make output as logic High Thus NMOS produces strong '0' and PMOS produces weak '0'.ĭifference between Pull up and Pull down Networks : If we use NMOS transistor then the voltage level of F is '0' V and if we use PMOS transistor then the voltage level of F is VTp i.e. For PDN the output should be pulled to logic low (i.e. Thus PMOS produces strong '1' and NMOS produces weak '1'.Ĭonsider the PDN constructed using PMOS and NMOS transistors as shown inįigure. Where VTn is threshold voltage of NMOS and if we use PMOS transistor then the voltage level of F is VDD. If we use NMOS transistor then the voltage level of F is VDD–VTn. For PUN the output should be pulled to logic high (i.e. In order to explain this concept consider the PUN constructed using PMOS and NMOS transistors as shown in Figure. The main reason for this combination is that NMOS transistors produce "strong zeros" and PMOS devices generate "strong ones". Normally the PDN is consisting of NMOS devices whereas PUN is consisting of PMOS devices. The PUN and PDN are complementary to each other. The function of PUN is to provide a connection between VDD and Vout to pull Vout to logic '1' whereas the function of PDN is to provide connection between GND and Vout to pull Vout to logic '0'. Figure below shows the 'N' input logic gate where all inputs are distributed to both the PUN and PDN. A complementary MOS gate is a combination of two networks the Pull Up Network (PUN) and the Pull Down Network (PDN).
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